A. Field of the Invention
This invention relates to the field of digital data processing systems wherein one or more host data processors utilize one or more supporting scientific processors in conjunction with storage systems that are commonly accessible. More particularly it relates to an improved High Performance Storage Unit (HPSU) memory resource for use in such a digital data processing system. Still more particularly it relates to an improvement according that such HPSU should be synchronously communicative with requestors, such host data processors and such scienrific processors, which are not of uniform interface cycle times, and furthermore that such HPSU should be synchronously communicative at non-uniform bit-widths of data transfer to such requestors.
B. State of the Prior Art
1. Environment of the Invention
Digital data processing systems are known wherein one or more independently operable data processors function with one or more commonly accessible main storage systems. Systems are also known that utilize a support processor with its associated dedicated supporting, or secondary storage system. Such support processors are often configured to perform specialized scientific computations and are commonly under task assignment control of one of the independently operable data processors. The controlling data processor is commonly referred to as a "host processor". The host processor characteristically functions to cause a task to be assigned to the support processor; to cause required instructions and data to be transferred to the secondary storage system; to cause the task execution to be initiated; and to respond to signals indicating the task has been completed, so that results can be transferred to the selected main storage systems. It is also the duty of the host processor to recognize and accommodate conflicts in usage and timing that might be detected to exist. Commonly, the host processor is free to perform other data processing matters while the support processor is performing its assigned tasks. It is also common for the host processor to respond to intermediate needs of the support processor, such as providing additional data if required, responding to detected fault conditions and the like.
In the past, support scientific data processors have been associated with host data processing systems. One such prior art scientific processor is disclosed in U.S. Pat. No. 4,101,960, entitled "Scientific Processor" and assigned to Burroughs Corporation, of Detroit, Mich. In that system, a single instruction multiple data processor, which is particularly suited for scientific applications, includes a high level language programmable front-end processor; a parallel task processor with an array memory; a large high speed secondary storage system having a multiplicity of high speed input/output channels commonly coupled to the front-end processor and to the array memory; and an overall control unit. In operation of that system, an entire task is transferred from the front-end processor to the secondary storage system whereupon the task is thereafter executed on the parallel task processor under the supervision of the control unit, thereby freeing the front-end processor to perform general purpose input/output operations and other tasks. Upon parallel task completion, the complete results are transferred back to the front-end processor from the secondary storage system.
It is believed readily seen that the front-end processor used in this earlier system is a large general purpose data processing system which has its own primary storage system. It is from this primary storage system that the entire task is transferred to the secondary storage system. Further, it is believed to be apparent that an input/output path exists to and from the secondary storage system from this front-end processor. Since task transfers involve the use of the input/output path of the front-end processor, it is this input/output path and the transfer of data thereon between the primary and secondary storage systems which becomes the limiting link between the systems. Such a limitation is not unique to the Scientific Processor as disclosed in U.S. Pat. No. 4,101,960. Rather, this input/output path and the transfers of data are generally considered to be the bottleneck in many such earlier known systems.
The present scienific data processing system is considered to overcome the data transfer bottleneck by providing an unique system architecture using a high speed memory unit which is commonly accessible by the host processor and the scientific processor. Further, when multiple high speed storage units are required, a multiple unit adapter is coupled between a plurality of high speed memory units and the scientific processor.
Data processing systems are becoming more and more complex. With the advent of integrated circuit fabrication technology, the cost per gate of logic elements is greatly reduced and the number of gates utilized is ever-increasing. A primary goal in architectural design is to improve the through-put of problem solutions. Such architectures often utilize a plurality of processing units in cooperation with one or more multiple port memory systems, whereby portions of the same problem solution may be parcelled out to different processors or different problems may be in the process of solution simultaneously.
2. Description of the Prior Art
Digital memories which communicate asynchronously or synchronously with requestors which have differing probabilities and prevalences of making repetitive requests separated by various time intervals are known in the prior art. The time or times of occurrence(s) of individual requests from requestors, or the latency time or times of the communication of data read responsively to such requests are not the subject of the present invention. The present invention synchronously communicates with plural types of requestors which plural requestor types do communicate at synchronous interface communication cycle times which are nonuniform, meaning different. The frequency that any one(s) of such requestors should make synchronous request of the present invention, and the latency(ies) thereafter such request that data read responsively thereto should be synchrnously communicated to such any one(s) of such requestors has nothing to do with the interface communication cycle times of each such information interchange of the request(s) and of the data read responsively to such request(s).
Digital memories which receive to be written, or which transmit as read, a data quantity which is but partial of the maximally exercisable bit-width of the interface communication channel(s) thereto such digital memories may be known in the prior art. The present invention is not concerned with data transfers occurring over but partial of the bit-width of a communication channel (although the present invention conventionally supports that but partial of the entire information, i.e., a quarter word or a half word, transmitted upon a communication channel should be used, as in a partial word write). The present invention is concerned with separate parallel communication channels, or interfaces, to a common shared digital computer memory resource, which separate interfaces do always have separate and unequal bit-widths of parallel data transfer thereupon. Certain prior art digital systems may employ a memory "A" of interface communication bit width "A.sup.1 ", and additionally a memory "B" of interface communication (even to the selfsome requestors) bit-width "B.sup.1 ". But the present invention is one single shared memory resource accessable on a priority basis by a multiplicity of requestors of a plurality of types which memory resource does communicate to some of said requestors at an interface communication bit-width of "A.sup.1 " and to others of said requestors at an interface communication bit-width of "B.sup.1 ".